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Integrated Circuit Systems, Inc.
ICS83840
DDR SDRAM MUX
FEATURES
* 40 low skew single-ended DIMM ports * 4 SSTL-2 compatible enable inputs * Maximum Switching Speed: 3ns * Output skew: 120ps (maximum) * Bank skew: 45ps (maximum) * ron = 8 (typical) * Full 2.5V supply modes * 0C to 70C ambient operating temperature * Pin compatible with the CBTV4010
GENERAL DESCRIPTION
The ICS83840 is a DDR SDRAM MUX and is a member of the HiPerClock STM family of High HiPerClockSTM Performance Clock Solutions from ICS. The device has 10 Host Lines and each host line can be passed to 4 Data Ports. The 10 channels are allocated as follows in the DDR SDRAM application: 8 data lines, 1 strobe line and 1 DQm line. The Host/Data Ports are compatible with single-ended SSTL-2 and the device operates from a 2.5V supply.
ICS
Guaranteed low output skew makes the ICS83840 ideal for demanding applications which require well defined performance and repeatability.
SIMPLIFIED SCHEMATIC
LOGIC DIAGRAM
HP0 RON Sw Sw Sw 0DP0 1DP0 2DP0 Sw 3DP0
HPx
nDPx
400
HP9 RON Sw Sw Sw Sw 0DP9 1DP9 2DP9 3DP9
nSn
SW
nS0 nS1 nS2
PIN ASSIGNMENT
1 A B C D E F G H J K L
2DP9 1DP9 0DP9 1DP8 0DP8 3DP7 VDD nS2 nc
nS3
4
GND
2
nS1 VDD nS3 GND 3DP9 HP9 3DP8 2DP8 HP8 GND 2DP7
3
nc nS0
5
1DP0 0DP0
6
2DP0 HP0
7
3DP0 0DP1
8
1DP1
9
2DP1 HP1
10
3DP1 GND HP2 3DP2 0DP3 HP 3 GND 0DP4 HP4
11
0DP2 1DP2 2DP2 1DP3 2DP3 3DP3 1DP4 2DP4 0DP5
REV. A DECEMBER 22, 2003
ICS83840
64-Ball TFBGA 7mm x 7mm x 1.2mm package body H Package Top View
HP7 1DP7
0DP7
3DP6 2DP6
HP6 1DP6
GND 0DP6
3DP5
HP5 2DP5
3DP4 1DP5
83840AH
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Integrated Circuit Systems, Inc.
ICS83840
DDR SDRAM MUX
TABLE 1. PIN DESCRIPTIONS
Number A1, B2 B4, B10, D2, G10, K2, K7 A 3, C 1 A2, B1, C2, B3 B6, B9, C10, F2, F10, J2, J10, K3, K6, K9 A5, A6, A7, B5 A9, A10, B7, B8 A11, B11, C11, D10 E10, E11, F11, G11 H10, J11, K10, K11 K8, L9, L10, L11 K5, L5, L6, L7 K4, L1, L2, L3 G2, H2, J1, K1 E1, E2, F1, G1 Name VDD GND nc nS1, nS2, nS3, nS0 HP0, HP1, HP2, HP9, HP3, HP8, HP4, HP7, HP6, HP5 1DP0, 2DP0, 3DP0, 0DP0 2DP1, 3DP1, 0DP1, 1DP1 0DP2, 1DP2, 2DP2, 3DP2 ODP3, 1DP3, 2DP3, 3DP3 0DP4, 1DP4, 3DP4, 2DP4 3DP5, 2DP5, 1DP5, 0DP5 3DP6, 2DP6, 1DP6, 0DP6 0DP7, 3DP7, 2DP7, 1DP7 3DP8, 2DP8, 1DP8, 0DP8 2DP9, 3DP9, 1DP9, 0DP9 Type Power Power Unused Por t Por t Por t Por t Por t Por t Por t Por t Por t Por t Por t Por t Description Positive supply pins. Power supply ground. No connect. Select pins. Host por ts. DIMM por ts. DIMM por ts. DIMM por ts. DIMM por ts. DIMM por ts. DIMM por ts. DIMM por ts. DIMM por ts. DIMM por ts. DIMM por ts.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter CIN CON Input Capacitance Channel on Capacitance nSx HP x Test Conditions VI = 0V or VDD VIN = 1.5V Minimum Typical Maximum 5 12 Units pF pF
NOTE: Capacitance values are measured at 10MHz and a bias voltage 3V. Capacitance is not production tested.
TABLE 3. FUNCTION TABLE
Control Input nSx L H Function Host Por t = DIMM Por t Host Por t = Disconnected DIMM Por t = 400 to GND
83840AH
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REV. A DECEMBER 22, 2003
Integrated Circuit Systems, Inc.
ICS83840
DDR SDRAM MUX
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Ports DC Input Clamp Current, IIK Package Thermal Impedance, JA Storage Temperature, TSTG -50mA 50.04C/W (0 mfps) -65C to 150C -0.5V to +3.3V -0.3V to VDD + 0.3 V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0C TO 70C
Symbol Parameter VDD IDD Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.3 Typical 2.5 Maximum 2.7 50 Units V A
TABLE 4B. DC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0C TO 70C
Symbol Parameter VIH VIL VIK IL Input High Voltage Input Low Voltage Input Clamp Voltage nSx Input Leakage Current Host Por t DIMM Por t rON On Resistance; NOTE 1 nSx nSx VDD = 2.3V; II = -18mA VDD = 2.5V; VI = VDD or GND; nS = VDD nS = GND for IIL(test) VDD = 2.5V; VA = 0.8V; VB = 1.0V 5 8 Test Conditions Minimum 1.6 0.9 -1.2 100 100 100 13 Typical Maximum Units V V V A A A
5 8 13 VDD = 2.5V; VA = 1.7V; VB = 1.5V NOTE 1: Measured by the current between the Host and the DIMM terminals at the indicated voltages on each side of the switch.
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0C TO 70C
Symbol Parameter Test Conditions Minimum Typical Maximum Units Propagation Delay; From HPx or xDPx to tPD 85 150 220 ps NOTE 1, 4 xDPx or HPx Output From nSx to 1.7 ns t EN Enable Time HPx or nDPx Output From nSx to tDIS 1.6 ns Disable Time HPx or nDPx Output Skew; Any Por t to any Por t 120 ps tOSK NOTE 2, 4 Bank Skew; Any Por t to any Por t 45 ps tBSK NOTE 3, 4 within the same bank NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew within a bank with equal load conditions. NOTE 4: Not production tested, guaranteed by characterization.
83840AH
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REV. A DECEMBER 22, 2003
Integrated Circuit Systems, Inc.
ICS83840
DDR SDRAM MUX
PARAMETER MEASUREMENT INFORMATION
VDD = 1.25V 0.1V
V DD
SCOPE
nDPx
V
DD
2
LVCMOS
GND
Qx
V
DD
nDPy
2 tsk(o)
-1.25V 0.1V
This circuit is used for test purposes only, not intended for application use.
2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
XDP0:XDP9
VDD 2
Sn (Low-level enabling)
2.5V 1.25V 1.25V 0V
XDP0:XDP9
VDD 2
tsk(o)
tPZH Output nDPx (See Note) 1.25V
tPHZ
VOH VOH - 0.15V VOL
NOTE: The output is high except when disabled by the Sn control.
BANK SKEW (where X denotes outputs in the same bank)
3-STATE OUTPUT ENABLE/DISABLE TIMES
D or H
VDD 2
H or D
t
PD
VDD 2
PROPAGATION DELAY
83840AH
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REV. A DECEMBER 22, 2003
Integrated Circuit Systems, Inc.
ICS83840
DDR SDRAM MUX RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
JA by Velocity (Millimeter Feet per Second) 0
Two-Layer PCB, JEDEC Standard Test Boards 50.04C/W
1
43.18C/W
2
41.17C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83840 is: 320
83840AH
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REV. A DECEMBER 22, 2003
Integrated Circuit Systems, Inc.
ICS83840
DDR SDRAM MUX
PACKAGE OUTLINE - H SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS FBGA SYMBOL A A1 A2 A3 b D D1 E E1 e MINIMUM NOMINAL MAXIMUM
64 Balls, 7x7mm, 11x11 Pattern 1.0 0.165 0.16 0.675 0.25 1.1 0.2 0.2 0.7 0.3 7.00 BSC 5.00 BSC 7.00 BSC 5.00 BSC 0.50 BSC 1.2 0.235 0.24 0.725 0.35
REFERENCE DOCUMENT: JEDEC PUBLICATION 95
83840AH
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REV. A DECEMBER 22, 2003
Integrated Circuit Systems, Inc.
ICS83840
DDR SDRAM MUX
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS83840AH ICS83840AHT ICS83840AHLF ICS83840AHLFT Marking ICS83840AH ICS83840AH ICS3840ALF ICS3840ALF Package 64-Ball TFBGA 64-Ball TFBGA on Tape and Reel 64-Ball, Lead Free, TFBGA 64-Ball, Lead Free, TFBGA on Tape and Reel Count 416 per tray 1000 416 per tray 1000 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83840AH
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REV. A DECEMBER 22, 2003
Integrated Circuit Systems, Inc.
ICS83840
DDR SDRAM MUX
REVISION HISTORY SHEET
Rev A
Table
Page 1 6 7
Description of Change Changed dimension on Pin Assignment from 0.7mm to 1.2mm. Updated Package Outline Drawing and Package Dimensions Table. Added "Lead Free" marking.
Date 12/22/03
83840AH
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REV. A DECEMBER 22, 2003

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